1. Field of the Invention The present invention relates to an interrupt controller for use in a microprocessor, which can handle a plurality of maskable interrupt requests.
2. Description of Related Art
Generally, systems using a microprocessor are provided with an interrupt controller so that, when an interrupt request is generated by a peripheral device in the course of execution of a program, the microprocessor discontinues the execution of the program being currently executed, and executes an interrupt processing program corresponding to the interrupt request generated by the peripheral device. Here, the program discontinued by the interrupt request will be called a "main program".
If a number of peripheral devices are coupled, a plurality of interrupt requests are concurrently generated, or when an interrupt program for an interrupt request of one peripheral device is being executed, another peripheral device generates an interrupt request. In order to comply with these situations, a multiple interrupt processing function is required to determine which of the concurrently generated interrupt requests should be acknowledged, and an interrupt mask function is also required for temporarily, reserving or suspending the interrupt request.
In addition, in compliance with conflict of a plurality of interrupt request signals, a priority order control is prepared to assign a different level of priority to each of the interrupt request signals, and to ensure that a processing program corresponding to an interrupt request signal having a high priority level is preferentially executed.
Furthermore, in order to execute one of the different interrupt processing programs corresponding to a plurality of interrupt requests, a mechanism can be provided to obtain a start address of each interrupt processing program. In a first case, the start address is fixed in accordance with the kind of interrupt requests, and in a second case, the start address is generated on the basis of information notified from the peripheral device (called a "vector number" hereinafter). In a third case, the functions of the first and second cases are selectively or simultaneously provided.
In addition, after execution of the interrupt processing program has been completed, it is necessary to return the control to the discontinued main program. For this purpose, there is provided a mechanism for preserving or saving information required to restart the main program (contents of register resources) after the interrupt request is acknowledged but before the control is moved to the interrupt processing program. A location where the information is preserved or saved, is in many cases in a stack of an internal or external memory section or in a register bank region.
In order to quickly perform the above mentioned various functions required for and associated with the interrupt, various microprocessors having the interrupt processing function have been proposed and reduced to practice. However, the following disadvantages have been encountered in connection with a plurality of maskable interrupt requests:
(1) External circuits including an interrupt controller have been required;
(2) Since a plurality of bus cycles are ceaselessly required, an interrupt responsiveness is low;
(3) Even in a conventional microprocessors in which the above has been improved, a multiple interrupt processing is not supported, and therefore, an interrupt responsiveness is dependent upon a program.